INSTRUCTION SET SIMULATOR GENERATION DEVICE AND SIMULATOR GENERATION METHOD

摘要

PROBLEM TO BE SOLVED: To provide a device that generates an ISS capable of quickly verifying the operation and execution time of an application program.;SOLUTION: The device has an application program reading means for reading in an application program that can run on an actual CPU, an execution stage instruction conversion means for converting the functions of instructions in the application program into one or more instructions to be simulated on a host CPU, a fetch stage instruction generation means for setting one or more instructions to simulate the operation timing of an instruction fetch stage out of pipeline stages of the actual CPU, before the execution stage instructions, and an ISS program output means for generating an instruction set simulator program according to the execution stage instructions and fetch stage instructions. The execution stage conversion means or fetch stage instruction generation means outputs counter instructions to simulate the clock of the actual CPU.;COPYRIGHT: (C)2007,JPO&INPIT