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Address translator, address translation method, and two-layer address translator

机译:地址转换器,地址转换方法和两层地址转换器

摘要

A first table stores operand data for translation of operand virtual address into a physical address. A second table stores instruction data for translation of instruction virtual address into a physical address. The first and the second tables are formed in one memory. If operand access and instruction access are generated simultaneously, the operand access is executed with priority and the instruction virtual address is held in a wait register after that the instruction access is executed after finishing the operand access based on a wait instruction virtual address.
机译:第一表存储用于将操作数虚拟地址转换为物理地址的操作数数据。第二表存储用于将指令虚拟地址转换为物理地址的指令数据。第一和第二表形成在一个存储器中。如果同时产生操作数访问和指令访问,则在基于等待指令虚拟地址完成操作数访问之后执行指令访问之后,将优先执行操作数访问并将指令虚拟地址保存在等待寄存器中。

著录项

  • 公开/公告号JP3970705B2

    专利类型

  • 公开/公告日2007-09-05

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP20020197952

  • 发明设计人 千葉 琢麻;本車田 強;山崎 巌;

    申请日2002-07-05

  • 分类号G06F12/10;G06F12/08;

  • 国家 JP

  • 入库时间 2022-08-21 21:08:52

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