Connection state detection circuit and IC chip built-in medium provided with the connection state detection circuit

摘要

PROBLEM TO BE SOLVED: To suppress the power consumption, and to improve the reliability. SOLUTION: When the applied timing signal from an IC control part 101 is in an enable condition, a PMOS transistor 20 for a pull-up resistor is in an energized condition through an inverter circuit 10. When a wire 80 to be detected is connected, the divided resistance voltage to be inputted in an AND circuit 70 through an intermediate lead is higher than the logical threshold at the AND circuit 70, and the connection condition signal to be outputted is on the HIGH level. When the wire 80 to be detected is disconnected, the divided resistance voltage to be inputted in the AND circuit 70 is only dependent on an NMOS transistor 60 for a pull-down resistor, and since the divided resistance voltage is lower than the logical threshold at the AND circuit 70, the connection condition signal to be outputted from the AND circuit 70 is on the LOW level. Thus, the connection or disconnection can be judged.