Bit timing of the digital detector circuit in order to regenerate the bit timing of the data stream and the mannered null data stream signal which controls

摘要

A digital detector circuit for recovering the bit timing of a data stream with a PLL includes a digital phase detector and a digital pulse length detector whose output signals are added and integrated, and the result is used for controlling the oscillator frequency. The output signal of the pulse length detector is determined by a corresponding algorithm, one slow and two fast, with direction-dependent output signals of the pulse length detector being generated.