PURPOSE:To realize high-speed writing and high-speed erasing by performing simultaneous data writing or erasing by using at least two out of separated plural sub-arrays and shifting the timing of data writing or erasing for another sub-array against that of data writing or erasing for desired sub-array. CONSTITUTION:While writing operation is made on a word line WL2r, reading operation for confirming writing is made on a word line WL 21, and while writing operation is made on the line WL 21, reading operation for confirming writing is made on the line WL2r. Then, when the threshold voltages of memory cells to be written out of selected memory cells M211 to M2n1 and M21r to M2nr reach all target values, the writing operation is completed thoroughly. Thus, high-speed writing and erasing can be realized.
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