Application of consistent cycle context for related setup and hold tests for static timing analysis

摘要

A technique for performing static timing analysis of an integrated circuit design provides a relationship between reference events of a setup test and a hold test for a particular signal path of an integrated circuit design. The relationship between the reference events of the setup and hold tests is used to compute a timing metric (e.g., slack) for at least one of the setup and hold tests to reduce the occurrence of timing escapes from the static timing analysis of the design. A static timing analyzer determines, with respect to edges of a reference signal, a signal capture event time for one of setup and hold timing metrics associated with a signal path. The capture event time is based on a capture event time for the other of the setup and hold timing metrics, a launch event time, and a test device type associated with the path.