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Binary stream switching controlled modulus divider for fractional frequency synthesis
Binary stream switching controlled modulus divider for fractional frequency synthesis
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机译:用于分数频率合成的二元流切换控制模数除法器
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摘要
A modulus divider controller coupled to a modulus divider for generating a synthesized clock from a reference clock, wherein the modulus divider generates a divided clock, is provided. The modulus divider controller may further include a first binary stream switching circuit having a first output and a second output. The first binary stream switching circuit may further have a logic low input and a logic high input and a first switching input corresponding to a most significant bit of a count generated by a synchronous counter, wherein the synchronous counter counts the divided clock. The first binary stream switching circuit may further have a second switching input corresponding to a least significant bit of a division control word, wherein the division control word specifies a fractional division ratio for the synthesized clock.
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