Frequency divider with improved linearity for a fractional-N synthesizer using a multi-modulus prescaler

摘要

A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N−1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus DN for each edge of the multi-modulus prescaler output clock CKpr wherein the counter samples the digital representation of D and DN denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.