Shift registers free of timing race boundary scan registers with two-phase clock control

摘要

A chain of boundary scan registers is configured to use a two-phase clock signal to avoid data timing race conditions. The two-phase clock signal is generated according to a two-phase clock generator, which includes two self-timed clock pulse generators for each boundary scan register. The two-phase clock generator locally generates a self-timed clock pulse at the rising edge of a clock signal, which triggers a first stage of the boundary scan register. The two-phase clock generator also generates a self-timed clock pulse at the falling edge of the input clock signal, which triggers a second stage of the boundary scan register. The two-phase clock controlled boundary scan register includes two latches, each latch is triggered by one of the self-timed clock pulse generated locally from the rising and falling edge of the input clock signal.