首页> 外国专利> Methods and apparatus for deskewing VCAT/LCAS members

Methods and apparatus for deskewing VCAT/LCAS members

机译:使VCAT / LCAS成员去偏斜的方法和设备

摘要

Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.
机译:写入逻辑和读取逻辑耦合到SDRAM和帧状态表。通过写逻辑将VCG成员写入SDRAM,并通过写逻辑为每个成员维护帧状态表中的条目(基于MFI和SQ)。读取逻辑扫描帧状态表,以识别SDRAM中可获得数据的最早帧号。基于帧状态和地址指针偏移,读取逻辑为每个VCG成员维护一个状态表条目,并为每个VCG维护一个状态。根据优选实施例,读取逻辑被提供为由临时缓冲器分开的两部分。读取逻辑的第一部分执行上述功能,并将块数据写入临时缓冲区。读取逻辑的第二部分根据可选的泄漏率从临时缓冲区读取字节数据。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号