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Hierarchical virtual model of a cache hierarchy in a multiprocessor system
Hierarchical virtual model of a cache hierarchy in a multiprocessor system
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机译:多处理器系统中缓存层次结构的层次虚拟模型
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摘要
The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.
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