首页>
外国专利>
System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel with translations of memory addresses
System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel with translations of memory addresses
展开▼
机译:通过与存储地址的转换并行地表征地址来避免页面冲突的系统,装置和方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
A system, apparatus, and method are disclosed for controlling accesses into memory to minimize sequential accesses to the same bank of memory, at least in part, by characterizing a subset of an address in parallel with address translations associated with those accesses. In one embodiment, an exemplary memory controller can include an address translator configured to translate an address useable by a processor to a first memory address. Also, the memory controller includes a bit characterizer configured to characterize a subset of the address as having a value from a range of values, and a bank separator coupled to the address translator and the bit characterizer for receiving a first portion of the first memory address and the value, respectively. Accordingly, the bank separator is configured to differentiate the first portion from a second portion of a second memory address.
展开▼