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Techniques for placing dummy features in an integrated circuit based on dielectric pattern density

机译:基于介电图案密度在集成电路中放置虚拟特征的技术

摘要

In one embodiment, a dummy pattern having a plurality of dummy features (e.g., waffles) are employed to help achieve a relatively planar surface by chemical-mechanical planarization (CMP). The dummy features are placed based on a dielectric pattern density of a region of an integrated circuit. The dummy features may be added to the design of the integrated circuit using a one pass or two pass approach. The dummy features in a second pass may be fragmented using an AndNot algorithm, for example.
机译:在一个实施例中,采用具有多个虚设特征(例如,华夫饼)的虚设图案以通过化学机械平坦化(CMP)帮助实现相对平坦的表面。基于集成电路区域的介电图案密度来放置伪部件。可以使用一遍或两遍方法将虚设特征添加到集成电路的设计中。例如,可以使用AndNot算法对第二遍中的伪特征进行分段。

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