An architecture for measurement of per-hop, one-way delay includes a input observation circuit (24) at the input interface of a node (12) and a output observation circuit (26) at the output interface (16) of a node (12). The input observation circuit (24) copies and time stamps the headers of incoming packets, and filters packets according to an aggregate definition. Similarly, the output observation circuit (26) copies and time stamps the headers of outgoing packets, and filters packets according to the aggregate definition. The incoming and outgoing traces are correlated to calculate a delay measurement. A packet loss measurement uses input observation circuits (72a and 72b) at the input interfaces (14) of upstream and downstream nodes (20 and 22) and an output observation circuit 74 at the output interface (16) of the upstream node. The observation circuits (72a, 72b and 74) determine the number of lost packets across a node and between nodes, according to an aggregate definition.
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机译：用于测量每跳单向延迟的体系结构包括在节点（ 12 ）的输入接口处的输入观察电路（ 24 ）和输出观察电路节点（ 12 ）的输出接口（ 16 ）上的（ 26 ）。输入观察电路（ 24 ）复制并标记传入数据包的标题，并根据汇总定义过滤数据包。同样，输出观察电路（ 26 ）复制并标记输出数据包的报头，并根据聚合定义过滤数据包。关联输入和输出轨迹以计算延迟测量。丢包测量使用输入接口（ 72 a 和 72 b ）的输入观察电路上游和下游节点（ 20 和 22 ）的> 14 ）和输出接口（ B> 16 ）。观察电路（ 72 a ，72 b 和 74 ）确定数量根据聚合定义，跨节点和节点之间丢失的数据包的数量。
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