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Asynchronous arbiter with bounded resolution time and predictable output state
Asynchronous arbiter with bounded resolution time and predictable output state
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机译:具有有限解析时间和可预测输出状态的异步仲裁器
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摘要
An arbiter circuit (100) can include a latch (106) that latches competing input signals (Req_A and Req_B) to generate latch output signals (latn1 and latn2). A filter section (108) can prevent metastable states of latch output signals (latn1 and latn2) from propagating through to output signals (Sel_A and Sel_B). If both input signals (Req_A and Req_B) are activated, a feedback circuit (110) can activate a feedback signal (fb) after a predetermined delay (δ), provided both output signals (Sel_A and Sel_B) remain inactive.
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