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Digital logic test method to systematically approach functional coverage completely and related apparatus and system
Digital logic test method to systematically approach functional coverage completely and related apparatus and system
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机译:完全系统地覆盖功能覆盖范围的数字逻辑测试方法及相关装置和系统
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摘要
A digital logic test method for systematically testing a pipeline-structured integrated circuit chip is disclosed. The method includes the steps of: providing an integrated circuit chip capable of executing a plurality of instructions during a period of time, each of the instructions being executed according to a plurality of sequentially ordered operation segments, sorting the instructions, and designing a plurality of test patterns to test the integrated circuit according to the sorting result and STAGE test segments corresponding to the STAGE operation segments.
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