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Chip-area reduction and congestion alleviation by timing-and-routability-driven empty-space propagation
Chip-area reduction and congestion alleviation by timing-and-routability-driven empty-space propagation
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机译:通过时序和可布线性驱动的空白空间传播来减少芯片面积并减少拥塞
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摘要
An EDA (Electronic Design Automation) process which collects and moves empty-spaces among cells on a circuit layout to one or more target areas for productive use, such as chip-size reduction and routability congestion alleviation. The process includes globally moving the empty-spaces to the target area and thereafter locally moving the empty-spaces as refinement.
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