首页>
外国专利>
Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control
Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control
展开▼
机译:通过独立的时钟和输出级控制来减少泄漏功耗的动态逻辑电路设备和方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed version of the logic clock and turns on the output inverter foot device after the dynamic node has had sufficient time to evaluate, providing a fast evaluate time and reducing leakage through the inverter input when the foot device is off. Alternatively, a coarsely timed static power control signal may be used to control the inverter foot devices. The drains of the inverter foot devices can be commonly connected across multiple circuits, reducing the foot device total area.
展开▼