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Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure

机译:半导体集成电路的布局方法,其布局结构以及用于形成布局结构的光掩模

摘要

A plurality of standard cells 10 are arranged to form a channel-less standard cell array 1, which has vertical and horizontal sides. A plurality of first proximity dummy cells 20 are arranged along each of the vertical sides of the standard cell array to form a first proximity dummy bands 20 such that the upper and lower sides of the first proximity dummy cells are in contact with each other and such that the left or right side of each of the first proximity dummy cells is in contact with the vertical side of the standard cell array 1. Furthermore, a plurality of second proximity dummy bands are arranged along each of the horizontal sides of the standard cell array to form a second proximity dummy bands such that the upper or lower side of each of the second proximity dummy cells is in contact with the horizontal side of the standard cell 1.
机译:布置多个标准单元 10 以形成具有垂直侧和水平侧的无通道标准单元阵列 1 。沿着标准单元阵列的每个垂直侧布置多个第一接近虚拟带 20 ,以形成第一接近虚拟带 20 ,使得上侧和下侧第一接近虚设单元中的每个第一接近虚设单元彼此接触,并且使得每个第一接近虚设单元的左侧或右侧与标准单元阵列 1 的垂直侧接触。此外,沿着标准单元阵列的每个水平侧布置多个第二接近虚拟带,以形成第二接近虚拟带,使得每个第二接近虚拟单元的上侧或下侧与水平接触。标准单元的侧面1。

著录项

  • 公开/公告号US7137092B2

    专利类型

  • 公开/公告日2006-11-14

    原文格式PDF

  • 申请/专利权人 JUN MAEDA;

    申请/专利号US20040914162

  • 发明设计人 JUN MAEDA;

    申请日2004-08-10

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 21:00:06

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