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Method and circuit for adjusting the timing of output data based on the current and future states of the output data
Method and circuit for adjusting the timing of output data based on the current and future states of the output data
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机译:用于基于输出数据的当前和未来状态来调整输出数据的时序的方法和电路
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摘要
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.
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