首页> 外国专利> EFFICIENT ENCODING OF LOW DENSITY PARITY CHECK (LDPC) CODES USING EXPANDED PARITY CHECK MATRICES

EFFICIENT ENCODING OF LOW DENSITY PARITY CHECK (LDPC) CODES USING EXPANDED PARITY CHECK MATRICES

机译:使用扩展奇偶校验矩阵的低密度奇偶校验(LDPC)编码的有效编码

摘要

A transmitter for a communications network, the transmitter comprising: receiving means for receiving data; accessing means for accessing a parity check code; generating means for generating encoded data including an error correction codeword using the data and the parity check code; and transmitting means for transmitting the encoded data and the error correction codeword, wherein the parity check code comprises a parity check matrix which, in expanded form, can be represented by the matrix H having the general structure Formula (I) wherein A, B, T, Q D and E represent sub-matrices, ET-1B being equal to the null matrix, the generating means comprising summing circuitry arranged to receive matrix elements ET-1 A and C to generate a sum, and matrix multiplication circuitry for receiving the sum, a matrix element D-1 and a matrix sT comprising the data, the matrix multiplication circuitry being operable to generate a parity part p1T of the error correction codeword according to the formula Formula (II).
机译:用于通信网络的发射机,该发射机包括:接收装置,用于接收数据;以及用于访问奇偶校验码的访问装置;生成装置,用于使用该数据和奇偶校验码生成包括纠错码字的编码数据;以及用于发送编码数据和纠错码字的发送装置,其中,奇偶校验码包括奇偶校验矩阵,该奇偶校验矩阵以扩展形式可以由具有通式(I)的通式H的矩阵H表示,其中,A,B, T,QD和E表示子矩阵,ET-1B等于空矩阵,生成装置包括:加法电路,被安排为接收矩阵元素ET-1A和C,以生成和;以及矩阵乘法电路,用于接收和矩阵矩阵D-1,包括数据的矩阵元素D-1和矩阵sT,矩阵乘法电路可用于根据公式(II)生成纠错码字的奇偶校验部分p1T。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号