METHOD OF REDUCING NOISE IN SIGMA-DELTA MODULATION USING DELAYED CLOCK SIGNALS AND FRACTIONAL-N PLL USING THE METHOD

摘要

A method of reducing noise in a sigma-delta modulation using delayed clock signals and a fractional divisional-type phase locked loop using the method are provided to reduce the noise without any effect to the transmitting function of sigma-delta modulator. A sigma-delta modulator(40) includes a delay circuit and an operating circuit. The delaying circuit(48) generates a plurality of the clock signals delayed as long as the delay of the standard clock signal. An operating circuit(41) includes a plurality of operating terminals and performs the high-level sigma-delta modulating operation by sequential operation of the plurality of the operating terminals according to the plurality of the clock signal. The operating circuit includes a latch and a quantizer, and operates the sigma-delta modulating operation by the interpolative-type.