ARRANGEMENT WITH A PLURALITY OF PROCESSORS HAVING AN INTERFACE FOR A COLLECTIVE MEMORY

摘要

The data processing apparatus of the present invention includes a memory interface which allows a plurality of processors and the processors can access a collective memory. The memory interface is an interface memory (SDRAM) for temporarily storing data belonging to different processors. Memory interface also to each other in a manner that forms a FIFO memory for each of the other processors, and a control circuit for controlling the interface memory. This makes it possible to conduct a relatively low cost as compared to a memory interface having a respective FIFO memory for each processor.