SYNCHRONOUS SEMICONDUCTOR MEMORY APPARATUS AND INPUT INFORMATION LATCH CONTROL METHOD THEEREOF

摘要

The object of the present invention is to provide a synchronous semiconductor memory device which can realize low current consumption by activating the input buffer circuit only for the operating cycle required without damaging the high-speed response of the input buffer. ; / CS, / RAS, / CAS, / WE, such as control signals (Control) in the combination is an active command (ACTV), a read command (READ, READA), the write command (WRITE, WRITEA), mode register command (MRS), free charge command (PRE) if the input is necessary due to the dynamic latch operation only command cycle iRAS signal at the rising edge of the iCLK signal is at a low level from the address pins of the light (Fig. 7), or iRAS on the rising edge of the iCLK signal or iCAS signal is output (Fig. 9), a latch signal in the case of a low level (aCLK) and latches the address and so on (Add).