A method for busan control in a device having a data on a bus system (bus1, bus2) issuing first circuit component (c) and on the bus system (bus1, bus2) joined other circuit components (p1 - pn, s1 - sn), wherein the data output on the bus system with different transfer rates, as a function of the speeds of the respective other circuit components (p1 - pn, s1 - sn), be transmitted via the bus system, characterized in that the first circuit component (c) an acknowledge signal (gx) is supplied to the completion of a data transfer taking place via the bus system, wherein the acknowledge signal (qx) by means of a logic operation of a release signal (clk _ en _ div _ x) and a selection signal (csx) is formed, wherein the enable signal a the nominal signal is ruggedly transfer rate, and the bus system according to the acknowledge signal (gx) following clock signal (clk _ div _ x) is released for further data transfer.
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机译：在具有在发布第一电路组件（c）的总线系统（bus1，bus2）上的数据以及在连接了其他电路组件（p1-pn，s1-sn）的总线系统（bus1，bus2）上的数据的设备中进行釜山控制的方法其中，通过总线系统传输在总线系统上以不同的传输速率输出的数据，该数据根据各个其他电路组件（p1-pn，s1-sn）的速度而变化，其特征在于，第一电路组件（c）通过总线系统将确认信号（gx）提供给完成的数据传输，其中，通过释放信号（clk_en_div_x）的逻辑运算来确认信号（qx） ）并形成选择信号（csx），其中使能信号a标称信号的传输速率很强，并且根据时钟信号（clk _ div _ x）之后的确认信号（gx）释放总线系统以进一步数据传输。
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