Controllable frequency splitter circuit, transmitter - receiver with a controllable frequency divider circuit and method for carrying out a loop - back - tests

摘要

Controllable frequency splitter circuit (1), comprising:– a signal input (10) in order to supply a clock signal (clk);– a signal output (11);– a first flip-flop - flop - circuit (2) with a clock input (clk), which, with the signal input (10) is coupled with a data input (d), with a first data output (q) for an output signal, and with a second data output (q) for a to the output signal inverted output signal;– at least one second flip-flop - flop - circuit (3) with a clock input (clk), which, with the signal input (10) is coupled with a data input (d), which together with the first data output (q) of the first flip-flop - flop - circuit (2), is connected to a first data output (q) for an output signal, and with a second data output (q) for a to the _Ausgangssignal inverted output signal with the formation of a feedback path with the data input (d) of the first flip-flop - flop - circuit (2) is coupled;– a multiplexer (5) with a first signal input (51), which together with the first data output (q) of the first flip flop circuit - -..