Field effect power component comprises a field effect element and an integral complementary metal oxide semiconductor structure surrounded by an outer trench structure

摘要

Field effect power component with a field effect element and an integral complementary metal oxide semiconductor (CMOS) structure comprises a low- to medium-doped n-type lateral drift zone on a complementarily doped substrate with an epitaxial layer with charge compensation zones in a trench structure that is filled with highly doped p-type polysilicon and has a wall (forming a pn transition zone with the drift zone. The field effect element and CMOS structure are surrounded by an outer trench structure and are separated from the substrate by a planar horizontal pn transition. Field effect power component with a field effect element (2) and an integral complementary metal oxide semiconductor (CMOS) structure (3) comprises a low- to medium-doped n-type lateral drift zone (4) on a complementarily doped substrate (5) with an epitaxial layer (6) with charge compensation zones (7) in a trench structure (8) that is filled with highly doped p-type polysilicon (9) and has a wall (10) forming a pn transition zone with the drift zone. The field effect element and CMOS structure are surrounded by an outer trench structure (29) and are separated from the substrate by a planar horizontal pn transition (12). An independent claim is also included for producing field effect power components with an integral complementary metal oxide semiconductor (CMOS) structure by preparing a weakly doped p-type semiconductor wafer substrate with semiconductor chip positions in cells and slots; selectively introducing a highly doped p-type zone, growing a low- to medium-doped n-type epitaxial layer, selectively introducing medium-doped p-type zones, introducing a trench structure, filling the trench structure with highly doped p-type polysilicon, forming pn transitions in the walls of the trench structure, selectively introducing highly doped n-type zones for the source and drain regions of the CMOS structure and the field effect element, selectively depositing a gate oxide layer over the body zones of the CMOS structure and the field effect element, selectively depositing highly doped n-type polysilicon on the gate oxide, performing additional insulation and metallization steps to complete the chips, separating the wafer into chips and packaging the chips in housing with external connectors.