The process involves forming a nano-wire (30) that has a contacting area (34), a control area (36) and a charge storage area (38) along a nano-wire longitudinal extension, where the storage area is formed as a part of a capacitor electrode. A control electrode is arranged on the control area of the nano-wire, and a capacitor dielectric (48) is arranged partially on the capacitor electrode. Another capacitor electrode is arranged partially on the capacitor dielectric. An independent claim is also included for a semiconductor memory device comprising a nano-wire.
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