Interface circuit for use in semiconductor memory chip, has serial input terminal to receive serial stream, and finite impulse response unit inserted into main write signal path between drift compensation FIFO-unit and serializer

摘要

The circuit has an interface circuit section with a serial input terminal to receive a serial stream of write data-/command. The interface circuit section has a drift compensation FIFO-unit (117) configured for compensating a phase drift of an even-odd bit aligned serial write data-/command. A finite impulse response (FIR) unit is inserted into a main write signal path between the drift compensation FIFO-unit and a serializer. A data input of a serial-to-parallel converter unit (14) is connected to an output of the de-emphasis FIFO-unit. Independent claims are also included for the following: (1) a semiconductor memory chip comprising a high-speed interface circuit (2) a semiconductor memory system comprising semiconductor memory chips.