Signal controlling circuit for serial peripheral interface bus-interface of microprocessor, has switching units for respectively activating clock and slave input lines and clock and slave output lines in response to select signal

摘要

The circuit (S) has connectors of an interface (I) for chip select (CS0-CS2) connected to respective connectors of the interface for a clock (CLK) and slave input (SI) via switching units (S11-S13) to transmit signals. The connectors of the interface for the chip select are connected to respective connectors of the interface for the clock and a slave output (SO) via other switching units to receive the signals. The switching units respectively activate clock lines (L11-L13) and slave input lines and the clock lines and slave output lines in response to a chip select signal. An independent claim is also included for a method for controlling a signal at a serial peripheral interface bus (SPI)-interface of a microprocessor.