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packaging waferebene using a mikrokappe with vias

机译:使用带有通孔的mikrokappe封装来华三烯

摘要

A microcap wafer-level package Ä10Ü is provided in which a micro device Ä14Ü is connected to bonding pads Ä16, 18Ü on a base wafer Ä12Ü. A peripheral pad Ä20Ü on the base wafer Ä12Ü encompasses the bonding pads Ä16, 18Ü and the micro device Ä14Ü. A cap wafer Ä24Ü is processed to form wells Ä40, 42Ü of a predetermined depth in the cap wafer Ä24Ü. A conductive material Ä27, 29Ü is made integral with the walls Ä46, 47Ü of the wells Ä40, 42Ü in the cap wafer Ä24Ü. The cap wafer Ä24Ü has contacts Ä30,32Ü and a peripheral gasket Ä22Ü formed thereon where the contacts Ä30,32Ü are capable of being aligned with the bonding pads Ä16, 18Ü on the base wafer Ä12Ü, and the gasket Ä22Ü matches the peripheral pad Ä20Ü on the base wafer Ä12Ü. The cap wafer Ä24Ü is then placed over the base wafer Ä12Ü so as to bond the contacts Ä30, 32Ü and gasket Ä22Ü to the pads Ä16, 18, 20Ü and form a hermetically sealed volume Ä25Ü within the peripheral gasket Ä22Ü. The cap wafer Ä24Ü is thinned to form a "microcap" Ä24Ü. The microcap Ä24Ü is thinned below the predetermined depth until the conductive material Ä27, 29Ü is exposed to become conductive vias Ä26, 28Ü through the cap wafer Ä24Ü to outside the hermetically sealed volume Ä25Ü. IMAGE
机译:提供了一个微帽晶圆级封装Ä10Ü,其中微型设备Ä14Ü连接到基础晶圆Ä12Ü上的键合焊盘Ä16、18Ü。基本晶圆Ä12Ü上的外围焊盘Ä20Ü包含接合焊盘Ä16、18Ü和微型设备Ä14Ü。处理盖晶片Ä24Ü,以在盖晶片Ä24Ü中形成预定深度的阱Ä40、42Ü。将导电材料Ä27、29Ü与盖晶片Ä24Ü中的孔Ä40、42Ü的壁Ä46、47Ü制成一体。盖片Ä24Ü上有触点Ä30,32Ü和外围垫片Ä22Ü,触点Ä30,32Ü能够与基础晶圆Ä12Ü上的键合焊盘Ä16、18Ü对准,垫片Ä22Ü与端片Ä20Ü上的外围垫片匹配基本晶圆Ä12Ü。然后将封口晶圆Ä24Ü放置在基础晶圆Ä12Ü上方,以便将触点Ä30、32Ü和垫片Ä22Ü粘结到焊盘Ä16、18、20Ü上,并在外围垫片Ä22Ü内形成密封体积Ä25Ü。薄晶圆Ä24Ü变薄以形成“微帽”Ä24Ü。将微帽Ä24Ü减薄到预定深度以下,直到将导电材料Ä27、29Ü暴露为穿过盖晶圆Ä24Ü到达密封容积Ä25Ü之外的导电通孔Ä26、28Ü。 <图像>

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