A memory tester (6) is equipped with History FIFO's (91-98, 124-127) whose depths are adjusted to account for the sum of the delays of the pipelines, relative to the location of that History FIFO's (91-98,124-127) whose depths are adjusted to accound for the sum of the delays of the pipelines, relation to the location of that History FIFO. When the error flag (90,99) is generated the desired program location and state information is present at the bottom of an appropriate History FIFO. This is also readily applicable when the test program uses an ALU to generate its own DUT stimuli, as well as to the case when the test program / ALU addresses an intermediate Buffer Memory whose contents are central to the nature of the testing the DUT is to undergo. The first is an ALU History FIFO (91-98), while the second is a Buffer Memory History FIFO (127-127). There can also be ECR History FIFO's. There is a mechanism (84) to track system re-configuration as it occurs and adjust the depths of the various History FIFO's according to resulting pipeline depth. There is a mechanism (86,98) to freeze the contents of a History FIFO upon the generation of an error. A History FIFO can be extended to allow a branching instruction in the test program to not prematurely respond to an error flag sooner than the pipeline delay needed for that error flag's value to be determined by a cause located within the test program. IMAGE
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