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TIMING VERIFICATION METHOD, TIMING VERIFICATION APPARATUS AND TIMING VERIFICATION PROGRAM

机译:时序验证方法,时序验证装置和时序验证程序

摘要

PPROBLEM TO BE SOLVED: To shorten the processing time of timing verification while ensuring accuracy. PSOLUTION: A timing verification method includes performing a timing analysis considering voltage drops of a circuit laid out (Step S70), and creating a modification instruction list for modifying the circuit laid out according to the timing analysis results (Step S90). In the first timing verification, a voltage drop analysis is performed for the circuit laid out (Step S40), a voltage drop list is created according to the voltage drop analysis results (Step S60), and the timing analysis is performed with the voltage drop list (Step S70). Meanwhile, in later timing verification, the voltage drop list is updated according to the modification instruction list (Step S100), and the timing analysis is performed with the updated voltage drop list (Step S70). PCOPYRIGHT: (C)2008,JPO&INPIT
机译:

要解决的问题:在确保准确性的同时,缩短时序验证的处理时间。

解决方案:时序验证方法包括:进行考虑布置的电路的电压降的时序分析(步骤S70);以及创建用于根据时序分析结果修改布置的电路的修改指令列表(步骤S90)。在第一时序验证中,对布置的电路执行电压降分析(步骤S40),根据电压降分析结果创建电压降列表(步骤S60),并利用电压降执行时序分析列表(步骤S70)。同时,在随后的时序验证中,根据修改指令列表来更新电压降列表(步骤S100),并且利用更新后的电压降列表来执行时序分析(步骤S70)。

版权:(C)2008,日本特许厅&INPIT

著录项

  • 公开/公告号JP2008112268A

    专利类型

  • 公开/公告日2008-05-15

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20060293920

  • 发明设计人 KOSUGI KAZUYUKI;

    申请日2006-10-30

  • 分类号G06F17/50;H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-21 20:24:28

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