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RECONFIGURABLE CIRCUIT, RECONFIGURABLE CIRCUIT SYSTEM AND PLACEMENT AND ROUTING METHOD OF RECONFIGURABLE CIRCUIT

机译:可重构电路,可重构电路系统以及可重构电路的布置和布线方法

摘要

PPROBLEM TO BE SOLVED: To solve the matter of a conventional reconfigurable circuit that since an ALU of multiple bits is occupied even when an enable signal of 1-bit is generated, many ALUs are needed resulting in enlargement of circuit scale. PSOLUTION: The reconfigurable circuit comprises a plurality of cells 10 each having a first selecting means 1 and a second selecting means 2 of K input 1 output, an ALU 4 for inputting outputs of N-bits from the first selecting means and the second selecting means and carrying out a specified arithmetic logical operation, a selection control means 3 which outputs a selection control signal Ss for specifying selection of the first selecting means and the second selecting means, and an ALU control means 5 which outputs an ALU control signal Sa for specifying an operation being carried out in the ALU, and means 21 and 22 for connecting respective cells through a network of bus. The first selecting means, the second selecting means and the ALU are reconfigurable, and the selection control signal controls the first selecting means and the second selecting means to output an i-th input while arranging its predetermined M[i] bits in a predetermined order. PCOPYRIGHT: (C)2009,JPO&INPIT
机译:

要解决的问题:为了解决传统的可重构电路的问题,由于即使在生成1位的使能信号时,由于也占用了多个位的ALU,因此需要许多ALU,从而导致电路规模的扩大。解决方案:可重构电路包括多个单元10,每个单元具有第一选择装置1和第二选择装置2,其具有K个输入1的输出,ALU 4用于输入来自第一选择装置的N位的输出,以及第二选择装置,并执行指定的算术逻辑运算;选择控制装置3,其输出用于指定第一选择装置和第二选择装置的选择的选择控制信号Ss;以及ALU控制装置5,其输出ALU控制信号Sa用于指定在ALU中执行的操作,以及用于通过总线网络连接各个单元的装置21和22。第一选择装置,第二选择装置和ALU是可重构的,并且选择控制信号控制第一选择装置和第二选择装置输出第i个输入,同时按预定顺序排列其预定的M [i]位。

版权:(C)2009,日本特许厅&INPIT

著录项

  • 公开/公告号JP2008235992A

    专利类型

  • 公开/公告日2008-10-02

    原文格式PDF

  • 申请/专利权人 MATSUSHITA ELECTRIC IND CO LTD;

    申请/专利号JP20070068559

  • 发明设计人 YAMANAKA RIYUUTAROU;

    申请日2007-03-16

  • 分类号H03K19/173;

  • 国家 JP

  • 入库时间 2022-08-21 20:24:03

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