LOGIC CIRCUIT REDESIGN PROGRAM, LOGIC CIRCUIT DESIGN DEVICE, AND LOGIC CIRCUIT REDESIGN METHOD

摘要

PPROBLEM TO BE SOLVED: To solve pin neck in dividing and redesigning a logic circuit into a plurality of FPGA or the like. PSOLUTION: A computer is made to perform pin information acquisition processing for acquiring a file showing information relating to a pin to be used by each port installed in each of the blocks of a logic circuit as the object of redesign and information showing the connection relation of mutual ports (#2), and perform multiplex circuit arrangement processing for arranging a multiplex circuit having a function for classifying the plurality of pins of the output port of a block into pin groups whose number is smaller than the number of pins, and for multiplexing a signal to be output from each of the pins classified into the same pin group based on the file (#11, #13), and perform separation circuit arrangement processing for arranging a separation circuit having a function for separating signals output from the output port of the block, and multiplexed by a multiplex circuit and a function for outputting each of the separated signals to the input port of the block at each input destination based on the file (#12, #13). PCOPYRIGHT: (C)2008,JPO&INPIT