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High-level synthesis equipment, hardware verification for model generation method, hardware verification method, control program and readable recording medium

机译:高级综合设备,模型生成方法的硬件验证,硬件验证方法,控制程序和可读记录介质

摘要

A high level synthesis device includes a high level synthesis section and a cycle accurate model. The high level synthesis section may perform high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components. The cycle accurate model may be configured to verify a state of at least one of the plurality of components and the controller at a cycle accurate level, with a general-purpose programming language.
机译:高级合成装置包括高级合成部分和周期精确模型。高级合成部可以执行包括多个组件和用于控制多个组件的控制器的硬件的高级合成。周期准确度模型可以被配置为使用通用编程语言以周期准确度验证多个组件和控制器中的至少一个的状态。

著录项

  • 公开/公告号JP4175953B2

    专利类型

  • 公开/公告日2008-11-05

    原文格式PDF

  • 申请/专利权人 シャープ株式会社;

    申请/专利号JP20030147025

  • 发明设计人 森下 貴弘;大西 充久;

    申请日2003-05-23

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 20:19:00

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