The operation result of 1 genera or more from operation circuit and aforementioned operation circuit the operation treatment circuit, the data storage circuit and the operation

摘要

PPROBLEM TO BE SOLVED: To attain the high speed acquisition of an arithmetic result by storing the arithmetic result obtained by executing an arithmetic operation in an arithmetic result memory which is different from a cache. PSOLUTION: In an arithmetic processing circuit, a cache 10 determines a cache hit error in response to a reading request from an instruction processing circuit 30, and the cache 10 outputs cache error information, when there is an error, to the instruction processing circuit 30. The instruction processing circuit 30 outputs a fill request to an external memory 50 according to the cache error information, and an external memory 50 outputs fill data. The cache 10 stores the fill data. An arithmetic circuit 40 performs an arithmetic operation to the fill data, and outputs the arithmetic result. An arithmetic result memory 20 stores the arithmetic result in a set corresponding to the set of the cache 10. The instruction processing circuit 30 reads the arithmetic result from the arithmetic result memory 20 in response to an arithmetic result reading instruction. PCOPYRIGHT: (C)2006,JPO&NCIPI