Power calculation device, power calculation method, tamper-resistant evaluation method and tamper-resistant evaluation device

摘要

The objective is to evaluate the tamper resistance of an actual circuit with high accuracy and high speed in the upstream process of circuit design. The tamper resistance evaluation apparatus calculates the power consumption of the logic circuit based on the signal change count counter 10 that counts the number of times the signal of the logic circuit has changed, and the number of changes in the signal counted by the signal change count counter. A file that stores a power consumption calculation unit 20, a leakage information analysis unit 80 that analyzes information leaked from the logic circuit based on the power consumption of the logic circuit calculated by the power consumption calculation unit, and a file that the simulator 30 uses Time series power information for generating time series power information in which the power consumption calculated by the power consumption calculation section 20 is arranged in time series, the database 40, the simulation control information generation section 50 for generating control information for controlling the logic simulator 30 A generation unit 60 and a result display unit 70 that displays time-series power information are provided.