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Encoding and decoding architecture and method for pipelining encoded data or pipelining with a look-ahead strategy
Encoding and decoding architecture and method for pipelining encoded data or pipelining with a look-ahead strategy
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机译:用于对编码的数据进行流水线处理或使用超前策略进行流水线处理的编码和解码架构及方法
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摘要
An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.
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