首页> 外国专利> SOI TRANSISTOR HAVING DRAIN AND SOURCE REGIONS OF REDUCED LENGTH AND A STRESSED DIELECTRIC MATERIAL ADJACENT THERETO

SOI TRANSISTOR HAVING DRAIN AND SOURCE REGIONS OF REDUCED LENGTH AND A STRESSED DIELECTRIC MATERIAL ADJACENT THERETO

机译:SOI晶体管的漏区和源区减小了长度,并在其中施加了应力的介电材料

摘要

By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.
机译:通过在SOI晶体管的漏极和源极区域中形成的凹槽中重新配置材料,可以在形成相应的金属硅化物区域之前将凹槽的深度增加到埋入绝缘层,从而降低了串联电阻并在相应的情况下增强了应力传递晶体管元件被高应力介电材料覆盖。可以基于高温氢烘烤来完成材料的重新分配。

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