首页> 外国专利> METHODS OF SYNCHRONOUS DIGITAL OPERATION AND SCAN BASED TESTING OF AN INTEGRATED CIRCUIT USING NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD

METHODS OF SYNCHRONOUS DIGITAL OPERATION AND SCAN BASED TESTING OF AN INTEGRATED CIRCUIT USING NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD

机译:基于负边缘翻转的Mussscan和边缘时钟兼容LSSD的集成电路的同步数字操作和基于扫描的测试方法

摘要

A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The method including: providing a flip-flop comprising: a master latch having an input and a clock pin; and a slave latch having an output, a first clock pin and a second clock pin; capturing data presented at said input of said master latch and transferring data stored in said master latch to said slave latch in response to a negative edge of a first clock signal on said clock pin of said master latch; launching data stored in said slave latch to said output of said slave latch in response to said negative edge of said first clock signal; and capturing data presented at said input of said master latch in response to a positive edge of a second clock signal on said clock pin of said master latch.
机译:一种使用触发器对集成电路进行同步数字操作和基于扫描的测试的方法。该方法包括:提供触发器,包括:具有输入和时钟引脚的主锁存器;从锁存器,其具有输出,第一时钟引脚和第二时钟引脚;响应于所述主锁存器的所述时钟引脚上的第一时钟信号的负沿,捕获呈现在所述主锁存器的所述输入处的数据,并将存储在所述主锁存器中的数据传输至所述从锁存器;响应于所述第一时钟信号的所述负沿,将存储在所述从锁存器中的数据启动到所述从锁存器的所述输出;响应于所述主锁存器的所述时钟引脚上的第二时钟信号的上升沿,捕获呈现在所述主锁存器的所述输入处的数据。

著录项

  • 公开/公告号US2008270863A1

    专利类型

  • 公开/公告日2008-10-30

    原文格式PDF

  • 申请/专利权人 DAVID E. LACKEY;

    申请/专利号US20080168210

  • 发明设计人 DAVID E. LACKEY;

    申请日2008-07-07

  • 分类号G01R31/3177;G06F11/25;

  • 国家 US

  • 入库时间 2022-08-21 20:14:03

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