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ANALYSIS TECHNIQUES TO REDUCE SIMULATIONS TO CHARACTERIZE THE EFFECT OF VARIATIONS IN TRANSISTOR CIRCUITS
ANALYSIS TECHNIQUES TO REDUCE SIMULATIONS TO CHARACTERIZE THE EFFECT OF VARIATIONS IN TRANSISTOR CIRCUITS
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机译:分析技术,可减少模拟以表征晶体管电路中变化的影响
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摘要
Embodiments of the invention provide a method, computer program product, etc. for analysis techniques to reduce simulations to characterize the effect of variations in transistor circuits. A method of simulating transistors in an integrated circuit begins by reducing a group of parallel transistors to a single equivalent transistor. The equivalent transistor is subsequently simulated, wherein only a portion of the parallel transistors are simulated. Next, the integrated circuit is divided into channel-connected components and simulated for the channel-connected components. A table is created for each type of channel-connected component; and parameterized across chip variation equations are calculated from results of the integrated circuit simulation. Moreover, table entries are created, which include a number of transistor types, a number of unique transistor primitive patterns, and/or a number of paths through each of the transistor primitive patterns.
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