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On-chip decoupling capacitance and power/ground network wire co-optimization to reduce dynamic noise
On-chip decoupling capacitance and power/ground network wire co-optimization to reduce dynamic noise
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机译:片上去耦电容和电源/接地网线共同优化以减少动态噪声
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摘要
A semiconductor power network (100) decoupling capacitance (decap) budgeting problem is co-optimized with a wiring enhancement problem, wherein the solution is formulated to minimize the total decap to be added or wiring changes (addition of wires (420)) to be made to the network (100). Voltage constraints, available white space and other constraints determine the amount of decap to be added. Wire enhancements and/or added decap can be distributed throughout a violation region (120) of the semiconductor circuit (100) design to reduce dynamic supply voltage noise so that dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level (220).
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