首页>
外国专利>
Four-gate transistor analog multiplier circuit
Four-gate transistor analog multiplier circuit
展开▼
机译:四栅极晶体管模拟乘法器电路
展开▼
页面导航
摘要
著录项
相似文献
摘要
A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.
展开▼