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Sense amplifier circuit and sense amplifier-based flip-flop having the same

机译:感测放大器电路和具有该感测放大器的基于触发器的触发器

摘要

A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluation signal pair corresponding to an input single pair to the first output terminal pair. The second latch latches the evaluation signal pair and outputs the evaluation signal pair to a second output terminal pair. The floating reduction unit is controlled by signals of the first output terminal pair and is operationally connected between current passing nodes of the first latch to prevent the first output terminal pair from floating. The input signal applying unit is disposed between the current passing nodes and a ground terminal, and receives the input signal pair. The ground switch is disposed between the input signal applying unit and the ground terminal, and is controlled by the clock signal. The delay reduction unit is disposed between the input signal applying unit and the ground switch, and reduces a signal delay from when the clock signal to when the evaluation signal pair is output from the second output terminal pair.
机译:基于感测放大器的触发器包括第一锁存器,第二锁存器,浮动减小单元,输入信号施加单元,接地开关和延迟减小单元。第一锁存器向第一输出端子对输出信号,并且将与输入单对对应的评估信号对输出至第一输出端子对。第二锁存器锁存评估信号对,并将评估信号对输出到第二输出端子对。浮动减小单元由第一输出端子对的信号控制,并且可操作地连接在第一锁存器的电流通过节点之间,以防止第一输出端子对浮动。输入信号施加单元设置在电流通过节点与接地端子之间,并接收输入信号对。接地开关设置在输入信号施加单元和接地端子之间,并由时钟信号控制。延迟减小单元设置在输入信号施加单元与接地开关之间,并且减小从时钟信号到第二输出端子对输出评估信号对之间的信号延迟。

著录项

  • 公开/公告号US7439775B2

    专利类型

  • 公开/公告日2008-10-21

    原文格式PDF

  • 申请/专利权人 YOUNG-SOO SOHN;

    申请/专利号US20070735694

  • 发明设计人 YOUNG-SOO SOHN;

    申请日2007-04-16

  • 分类号G01R19/00;G11C7/00;H03F3/45;

  • 国家 US

  • 入库时间 2022-08-21 20:11:52

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