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High speed early/late discrimination systems and methods for clock and data recovery receivers
High speed early/late discrimination systems and methods for clock and data recovery receivers
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机译:用于时钟和数据恢复接收器的高速早期/晚期鉴别系统和方法
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摘要
The present invention facilitates clock and data recovery for serial data streams by providing a mechanism that can be employed to detect and adjust operation and timing of clocks. The invention employs a differential analog circuit, using current steering logic, to process center and edge samples and identify an average operation of the clocks. The circuit can identify transitions between adjacent center/edge data samples and determine whether an identified transition is early or late for each bit in a set of consecutive bits of a received serial data stream.
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