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High performance RISC instruction set digital signal processor having circular buffer and looping controls
High performance RISC instruction set digital signal processor having circular buffer and looping controls
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机译:具有循环缓冲区和循环控制的高性能RISC指令集数字信号处理器
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摘要
A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seem less transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low-overhead interrupts.
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