RISP: A digital signal processor architecture with reduced instruction set tailored to wave digital filters

摘要

VLSI in digital signal processing requires small, stable, high-speed infinite impulse response (IIR) filters. A novel DSP architecture, RISP (reduced instruction set processor), has been designed. It incorporates a reduced-instruction set to minimize instruction cycle time, a three-stage pipeline, small transistor count and specialized blocks enabling high throughput for wave digital filter (WDF) algorithms, including decimation and interpolation. The RISP architecture has been verified by means of a dedicated CAD system including the top-down design of lattice WDFs from specification to RISP machine code.