Wafer level chip scale package (WLCSP) with high reliability against thermal stress

摘要

A wafer level chip scale package includes a semiconductor chip having a plurality of pads; a lower insulation layer having a high Young's modulus of 1˜5 GPa formed on the semiconductor chip to expose the plurality of pads; a plurality of metal patterns formed on the lower insulation layer to be connected to the respective pads; an upper insulation layer having a high Young's modulus of 1˜5 GPa formed on the lower insulation layer and the metal patterns to partially expose the metal patterns; and a plurality of solder balls formed on exposed portions of the metal patterns.