a device (43) for generating pseudo-random address values to be applied to corresponding address inputs of a semi-conductor component (2b), in particular a memory component, to be tested."/> Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure
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Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure

机译:半导体元件测试装置,特别是具有半导体元件测试装置的数据缓冲元件,以及半导体元件测试程序

摘要

The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise:a device (43) for generating pseudo-random address values to be applied to corresponding address inputs of a semi-conductor component (2b), in particular a memory component, to be tested.
机译:本发明涉及一种半导体元件测试程序以及一种半导体元件测试装置( 10 b ),包括: 用于生成伪随机地址值的设备( 43 ),该设备将应用于半导体组件( 2 b ),尤其是要测试的内存组件。

著录项

  • 公开/公告号US7421629B2

    专利类型

  • 公开/公告日2008-09-02

    原文格式PDF

  • 申请/专利权人 THORSTEN BUCKSCH;MARTIN MEIER;

    申请/专利号US20050253814

  • 发明设计人 MARTIN MEIER;THORSTEN BUCKSCH;

    申请日2005-10-20

  • 分类号G11C29/00;

  • 国家 US

  • 入库时间 2022-08-21 20:10:20

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